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W28F641B/t 64mbit (4mbit 16) page mode dual work flash memory publication release date: march 27, 2003 - 1 - revision a3 table of contents- 1. general d escription ......................................................................................................... ......... 2 2. features .................................................................................................................... ..................... 2 3. pin conf igurati on ........................................................................................................... ............ 3 4. electrical characteristics ................................................................................................. 1 6 absolute maxi mum rati ngs* ...................................................................................................... ...... 16 operating conditi ons ........................................................................................................... ............. 16 capacitance (1) ............................................................................................................................... ... 17 ac input/output test c onditions ................................................................................................ ...... 17 dc characte ristics ............................................................................................................. ............... 18 ac characteristics - read-only operat ions(1 ) ................................................................................. 20 ac characteristics - write operations (1, 2) ...................................................................................... 23 reset oper ations ............................................................................................................... ............... 25 reset ac spec ificat ions ........................................................................................................ ........... 25 block erase, full chip erase, (page bu ffer) program and otp program performance (3) ............. 26 5. additional informat ion ...................................................................................................... ..... 27 recommended operati ng conditi ons .............................................................................................. 2 7 at device power-u p ............................................................................................................. ...... 27 glitch noises .................................................................................................................. ............ 28 6. ordering informat ion ........................................................................................................ ..... 29 7. package di mensio ns .......................................................................................................... ....... 30 48-pin standard thin small outline package (measured in millimet ers) ......................................... 30 48-ball tfbga (8 mm x 11 mm) (m easurements in millimeter s) ..................................................... 30 8. version history ............................................................................................................. ............ 31
W28F641B/t 1. general description the w28f641, a 4-plane page mode dual work (s imultaneous read while erase/program) flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can be operated at v dd = 2.7v to 3.6v and v pp = 1.65v to 3.6v o r 11.7v to 12.3v. its low voltage operation capabilit y greatly extends battery life for portable applications. the w28f641 provides high performance asynchronous page mode. it allows code execution directly from flash, thus eliminating time-consuming wait states. furthermore, the configurative partitioning architecture allows flexible dual work operation. the memory array block architecture utilizes enhanced data protection features, and provides separate parameter and main blocks that provide maximum flexibility for safe nonvolatile code and data storage. fast program capability is provided through the us e of high speed page buffer program. special otp (one time program) block provides an area to store permanent code such as a unique number. 2. features one hundred and twenty-seven 32k-word main b l ocks x 64m dens ity with 16bit i/o interfac e x high-performance reads top or bottom parameter location 80/35 ns 8-word page mode x enhanced data protection features x configurative 4-plane dual work individual block lock and block lock-down with zero-latency flexible partitioning read operations during block erase or (page buffer) program a ll blocks are locked at power-up or dev ice reset status register for each partition abs o lute protec tion with v pp d v pplk x low power operation block erase, full chip erase, (page buffer) word program lockout during power transitions 2.7v read and write operations v ddq for input/output power supply isolation automatic power savings mode reduces i ccr in static mode x automated erase/program algorithms 3.0v low-power 11 p s/ word (ty p .) programming x enhanced code + data storage 5 p s typical erase/program suspends 12v no glue logic 9 p s/ word (ty p .) production programming and 0.5s erase (ty p .) x otp (one time program) block 4-word factory-programmed area 4-word user-programmable area x cross-compatible command support x high performance program with page buffer common flash interface (cfi) basic command set 16-word page buffer 5 p s/ word (typ.) at 12v v pp x extended cycling capability x operating temperature minimum 100,000 block erase cycles -40 q c to + 8 5 q c x chip-size packaging x cmos process (p-type silicon substrate) 0.75 mm pitch 48-ball tfbga and 48-pin tsop x flexible blocking architecture x etox? flash technology e i ght 4k-word p a ramet e r b l ocks - 2 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 x no designed or rated as radiation hardened * etox is a tradem ark of intel corporation. 3. pin configuration a #ce a3 b c d e f g h a4 a2 a1 a0 #oe a7 a17 a6 a5 dq0 dq8 dq9 dq1 a18 a20 dq2 dq10 dq11 dq3 #wp #we #reset a21 a19 dq5 dq12 v ddq dq4 a9 a8 a10 a11 dq7 dq14 dq13 dq6 a13 a12 a14 a15 a16 dq15 vss vss v dd v pp 1 2 3 4 5 6 48-pin tsop standard pinout 12mm x 20mm top view dq15 #oe a16 #ce a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v dd dq7 dq14 dq6 dq13 dq5 dq12 dq4 v vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a9 a10 a11 a12 a13 a14 a15 24 23 a17 #we a7 a6 a5 a4 a3 a2 a1 21 22 #wp a18 a19 #reset a20 a21 a8 v pp ddq 0.75 mm pitch 48-ball tfbga pinout 8 x 11 mm top view figure 1. 0.75 mm pitch tfbga 48-ball and 48-lead tsop (normal bend) pinout - 3 - revi si on a3
W28F641B/t table 1. pin descriptions symbol type na me a nd function a0 a21 input a ddress inputs : inputs for addresses. 64m: a0 a21. dq0 dq15 input / out p ut da ta input/outputs : inputs data and commands dur ing cui (command user interface) w r ite cy cles, outputs data during memory array , status register, query code, identifier code and partition conf iguration register code reads. data pins float to high impedance (high z ) w hen the chip or outputs are deselected. data is internally latched during an erase or program cy cle. # c e i n p u t chip ena b le : activates the device?s control logic, input buffers, decoders and sense amplifiers. #ce-high (v ih ) deselects the device and reduces pow er consumption to standby levels. #reset i n p u t reset : w hen low (v il ), #reset resets internal automation and inhibits w r ite operations, w h ich provides dat a protection. #reset -high (v ih ) enables normal operation. after pow er-up or reset mode, the device is automatically set to read array mode. #reset must be low during pow er-up/dow n. # o e i n p u t output ena b le : gates the device?s outputs during a read cy cle. # w e i n p u t write ena b le : controls w r ites to the cui and array blocks. addresses and data are latched on the rising edge of #ce or #w e (w hichever goes high first). # w p i n p u t write protect : w hen #w p is v il , locked-dow n blocks cannot be unlocked. erase or program operation can be ex ecuted to the blocks w h ich are not locked and not locked-dow n. w hen #w p is v ih , lock-dow n is disabled. v pp i n p u t monitoring power supply volta ge: v pp is not used for pow er supply pin. with v pp d v pplk , block erase, full chip erase, (page buffer) program or ot p program cannot be executed and shoul d not be attempted. apply i ng 12v 0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is pow er supply pin. apply i ng 12v 0.3v to v pp during erase/program can only be done for a maximum of 1,000 cy cles on each block. v pp may be connected to 12v 0.3v for a total of 80 hours maximum. use of this pin at 12v bey ond these limits may reduce block cy cling c apability or cause permanent damage. v dd s u p p l y device power supply : with v dd d v lko , all w r ite attempts to the flash memory are inhibited. device operations at invalid v dd voltage (see dc characteristics) produce spurious results and should not be attempted. v ddq s u p p l y input/output power supply (2.7v to 3.6v): pow e r supply for all input/output pins. v ss s u p p l y ground : do not float any ground pins. - 4 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 table 2. simultaneous operation modes allow e d w i th four planes (1,2) then the modes a llowed in the other pa rtition is: if one pa rtition is: read a rray read id/otp read status read quer y wo rd program page buffer program otp program block erase full chip erase program suspend block erase suspend read array x x x x x x x x x read id/ot p x x x x x x x x x read status x x x x x x x x x x x read query x x x x x x x x x w o r d p r ogr am x x x x x page buffer program x x x x x ot p p r o g r a m x b l oc k e r as e x x x x full chip erase x program suspend x x x x x block erase suspend x x x x x x x notes: 1. "x" denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write state machine) state - this allow s a status register for each partitio n. only one partition can be erased or progr ammed at a time - no command queuing. commands must be w r itten to an address w i thin the block targeted by that command. - 5 - revi si on a3
W28F641B/t blo ck number a ddress ra ng e 134 4k- w o rd 3ff000h - 3fffffh 133 4k- w o rd 3fe000h - 3fefffh 132 4k- w o rd 3fd000h - 3fdfffh 131 4k- w o rd 3fc000h - 3fcfffh 130 4k- w o rd 3fb000h - 3fbfffh 129 4k- w o rd 3fa000h - 3fafffh 128 4k- w o rd 3f9000h - 3f9fffh 127 4k- w o rd 3f8000h - 3f8fffh 126 32k- w o rd 3f0000h - 3f7fffh 125 32k- w o rd 3e8000h - 3effffh 124 32k- w o rd 3e0000h - 3e7fffh 123 32k- w o rd 3d8000h - 3dffffh 122 32k- w o rd 3d0000h - 3d7fffh 121 32k- w o rd 3c8000h - 3cffffh 120 32k- w o rd 3c0000h - 3c7fffh 119 32k- w o rd 3b8000h - 3bffffh 118 32k- w o rd 3b0000h - 3b7fffh 117 32k- w o rd 3a8000h - 3affffh 116 32k- w o rd 3a0000h - 3a7fffh 115 32k- w o rd 398000h - 39ffffh 114 32k- w o rd 390000h - 397fffh 113 32k- w o rd 388000h - 38ffffh 112 32k- w o rd 380000h - 387fffh 111 32k- w o rd 378000h - 37ffffh 110 32k- w o rd 370000h - 377fffh 109 32k- w o rd 368000h - 36ffffh 108 32k- w o rd 360000h - 367fffh 107 32k- w o rd 358000h - 35ffffh 106 32k- w o rd 350000h - 357fffh 105 32k- w o rd 348000h - 34ffffh 104 32k- w o rd 340000h - 347fffh 103 32k- w o rd 338000h - 33ffffh 102 32k- w o rd 330000h - 337fffh 101 32k- w o rd 328000h - 32ffffh 100 32k- w o rd 320000h - 327fffh 99 32k- w o rd 318000h - 31ffffh 98 32k- w o rd 310000h - 317fffh 97 32k- w o rd 308000h - 30ffffh plane3 (parameter plane) 96 32k- w o rd 300000h - 307fffh 95 32k- w o rd 2f8000h - 2fffffh 94 32k- w o rd 2f0000h - 2f7fffh 93 32k- w o rd 2e8000h - 2effffh 92 32k- w o rd 2e0000h - 2e7fffh 91 32k- w o rd 2d8000h - 2dffffh 90 32k- w o rd 2d0000h - 2d7fffh 89 32k- w o rd 2c8000h - 2cffffh 88 32k- w o rd 2c0000h - 2c7fffh 87 32k- w o rd 2b8000h - 2bffffh 86 32k- w o rd 2b0000h - 2b7fffh 85 32k- w o rd 2a8000h - 2affffh 84 32k- w o rd 2a0000h - 2a7fffh 83 32k- w o rd 298000h - 29ffffh 82 32k- w o rd 290000h - 297fffh 81 32k- w o rd 288000h - 28ffffh 80 32k- w o rd 280000h - 287fffh 79 32k- w o rd 278000h - 27ffffh 78 32k- w o rd 270000h - 277fffh 77 32k- w o rd 268000h - 26ffffh 76 32k- w o rd 260000h - 267fffh 75 32k- w o rd 258000h - 25ffffh 74 32k- w o rd 250000h - 257fffh 73 32k- w o rd 248000h - 24ffffh 72 32k- w o rd 240000h - 247fffh 71 32k- w o rd 238000h - 23ffffh 70 32k- w o rd 230000h - 237fffh 69 32k- w o rd 228000h - 22ffffh 68 32k- w o rd 220000h - 227fffh 67 32k- w o rd 218000h - 21ffffh 66 32k- w o rd 210000h - 217fffh 65 32k- w o rd 208000h - 20ffffh plane2 (uniform plane) 64 32k- w o rd 200000h - 207fffh blo ck number a ddress ra ng e 63 32k- w o rd 1f8000h - 1fffffh 62 32k- w o rd 1f0000h - 1f7fffh 61 32k- w o rd 1e8000h - 1effffh 60 32k- w o rd 1e0000h - 1e7fffh 59 32k- w o rd 1d8000h - 1dffffh 58 32k- w o rd 1d0000h - 1d7fffh 57 32k- w o rd 1c8000h - 1cffffh 56 32k- w o rd 1c0000h - 1c7fffh 55 32k- w o rd 1b8000h - 1bffffh 54 32k- w o rd 1b0000h - 1b7fffh 53 32k- w o rd 1a8000h - 1affffh 52 32k- w o rd 1a0000h - 1a7fffh 51 32k- w o rd 198000h - 19ffffh 50 32k- w o rd 190000h - 197fffh 49 32k- w o rd 188000h - 18ffffh 48 32k- w o rd 180000h - 187fffh 47 32k- w o rd 178000h - 17ffffh 46 32k- w o rd 170000h - 177fffh 45 32k- w o rd 168000h - 16ffffh 44 32k- w o rd 160000h - 167fffh 43 32k- w o rd 158000h - 15ffffh 42 32k- w o rd 150000h - 157fffh 41 32k- w o rd 148000h - 14ffffh 40 32k- w o rd 140000h - 147fffh 39 32k- w o rd 138000h - 13ffffh 38 32k- w o rd 130000h - 137fffh 37 32k- w o rd 128000h - 12ffffh 36 32k- w o rd 120000h - 127fffh 35 32k- w o rd 118000h - 11ffffh 34 32k- w o rd 110000h - 117fffh 33 32k- w o rd 108000h - 10ffffh plane1 (uniform plane) 32 32k- w o rd 100000h - 107fffh 31 32k- w o rd 0f8000h - 0fffffh 30 32k- w o rd 0f0000h - 0f7fffh 29 32k- w o rd 0e8000h - 0effffh 28 32k- w o rd 0e0000h - 0e7fffh 27 32k- w o rd 0d8000h - 0dffffh 26 32k- w o rd 0d0000h - 0d7fffh 25 32k- w o rd 0c8000h - 0cffffh 24 32k- w o rd 0c0000h - 0c7fffh 23 32k- w o rd 0b8000h - 0bffffh 22 32k- w o rd 0b0000h - 0b7fffh 21 32k- w o rd 0a8000h - 0affffh 20 32k- w o rd 0a0000h - 0a7fffh 19 32k- w o rd 098000h - 09ffffh 18 32k- w o rd 090000h - 097fffh 17 32k- w o rd 088000h - 08ffffh 16 32k- w o rd 080000h - 087fffh 15 32k- w o rd 078000h - 07ffffh 14 32k- w o rd 070000h - 077fffh 13 32k- w o rd 068000h - 06ffffh 12 32k- w o rd 060000h - 067fffh 11 32k- w o rd 058000h - 05ffffh 10 32k- w o rd 050000h - 057fffh 9 32k- w o rd 048000h - 04ffffh 8 32k- w o rd 040000h - 047fffh 7 32k- w o rd 038000h - 03ffffh 6 32k- w o rd 030000h - 037fffh 5 32k- w o rd 028000h - 02ffffh 4 32k- w o rd 020000h - 027fffh 3 32k- w o rd 018000h - 01ffffh 2 32k- w o rd 010000h - 017fffh 1 32k- w o rd 008000h - 00ffffh plane0 (uniform plane) 0 32k- w o rd 000000h - 007fffh figure 2.1 top parameter memory map - 6 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 blo ck number a ddress ra ng e 134 32k- w o rd 3f8000h - 3fffffh 133 32k- w o rd 3f0000h - 3f7fffh 132 32k- w o rd 3e8000h - 3effffh 131 32k- w o rd 3e0000h - 3e7fffh 130 32k- w o rd 3d8000h - 3dffffh 129 32k- w o rd 3d0000h - 3d7fffh 128 32k- w o rd 3c8000h - 3cffffh 127 32k- w o rd 3c0000h - 3c7fffh 126 32k- w o rd 3b8000h - 3bffffh 125 32k- w o rd 3b0000h - 3b7fffh 124 32k- w o rd 3a8000h - 3affffh 123 32k- w o rd 3a0000h - 3a7fffh 122 32k- w o rd 398000h - 39ffffh 121 32k- w o rd 390000h - 397fffh 120 32k- w o rd 388000h - 38ffffh 119 32k- w o rd 380000h - 387fffh 118 32k- w o rd 378000h - 37ffffh 117 32k- w o rd 370000h - 377fffh 116 32k- w o rd 368000h - 36ffffh 115 32k- w o rd 360000h - 367fffh 114 32k- w o rd 358000h - 35ffffh 113 32k- w o rd 350000h - 357fffh 112 32k- w o rd 348000h - 34ffffh 111 32k- w o rd 340000h - 347fffh 110 32k- w o rd 338000h - 33ffffh 109 32k- w o rd 330000h - 337fffh 108 32k- w o rd 328000h - 32ffffh 107 32k- w o rd 320000h - 327fffh 106 32k- w o rd 318000h - 31ffffh 105 32k- w o rd 310000h - 317fffh 104 32k- w o rd 308000h - 30ffffh plane3 (uniform plane) 103 32k- w o rd 300000h - 307fffh 102 32k- w o rd 2f8000h - 2fffffh 101 32k- w o rd 2f0000h - 2f7fffh 100 32k- w o rd 2e8000h - 2effffh 99 32k- w o rd 2e0000h - 2e7fffh 98 32k- w o rd 2d8000h - 2dffffh 97 32k- w o rd 2d0000h - 2d7fffh 96 32k- w o rd 2c8000h - 2cffffh 95 32k- w o rd 2c0000h - 2c7fffh 94 32k- w o rd 2b8000h - 2bffffh 93 32k- w o rd 2b0000h - 2b7fffh 92 32k- w o rd 2a8000h - 2affffh 91 32k- w o rd 2a0000h - 2a7fffh 90 32k- w o rd 298000h - 29ffffh 89 32k- w o rd 290000h - 297fffh 88 32k- w o rd 288000h - 28ffffh 87 32k- w o rd 280000h - 287fffh 86 32k- w o rd 278000h - 27ffffh 85 32k- w o rd 270000h - 277fffh 84 32k- w o rd 268000h - 26ffffh 83 32k- w o rd 260000h - 267fffh 82 32k- w o rd 258000h - 25ffffh 81 32k- w o rd 250000h - 257fffh 80 32k- w o rd 248000h - 24ffffh 79 32k- w o rd 240000h - 247fffh 78 32k- w o rd 238000h - 23ffffh 77 32k- w o rd 230000h - 237fffh 76 32k- w o rd 228000h - 22ffffh 75 32k- w o rd 220000h - 227fffh 74 32k- w o rd 218000h - 21ffffh 73 32k- w o rd 210000h - 217fffh 72 32k- w o rd 208000h - 20ffffh plane2 (uniform plane) 71 32k- w o rd 200000h - 207fffh blo ck number a ddress ra ng e 70 32k- w o rd 1f8000h - 1fffffh 69 32k- w o rd 1f0000h - 1f7fffh 68 32k- w o rd 1e8000h - 1effffh 67 32k- w o rd 1e0000h - 1e7fffh 66 32k- w o rd 1d8000h - 1dffffh 65 32k- w o rd 1d0000h - 1d7fffh 64 32k- w o rd 1c8000h - 1cffffh 63 32k- w o rd 1c0000h - 1c7fffh 62 32k- w o rd 1b8000h - 1bffffh 61 32k- w o rd 1b0000h - 1b7fffh 60 32k- w o rd 1a8000h - 1affffh 59 32k- w o rd 1a0000h - 1a7fffh 58 32k- w o rd 198000h - 19ffffh 57 32k- w o rd 190000h - 197fffh 56 32k- w o rd 188000h - 18ffffh 55 32k- w o rd 180000h - 187fffh 54 32k- w o rd 178000h - 17ffffh 53 32k- w o rd 170000h - 177fffh 52 32k- w o rd 168000h - 16ffffh 51 32k- w o rd 160000h - 167fffh 50 32k- w o rd 158000h - 15ffffh 49 32k- w o rd 150000h - 157fffh 48 32k- w o rd 148000h - 14ffffh 47 32k- w o rd 140000h - 147fffh 46 32k- w o rd 138000h - 13ffffh 45 32k- w o rd 130000h - 137fffh 44 32k- w o rd 128000h - 12ffffh 43 32k- w o rd 120000h - 127fffh 42 32k- w o rd 118000h - 11ffffh 41 32k- w o rd 110000h - 117fffh 40 32k- w o rd 108000h - 10ffffh plane1 (uniform plane) 39 32k- w o rd 100000h - 107fffh 38 32k- w o rd 0f8000h - 0fffffh 37 32k- w o rd 0f0000h - 0f7fffh 36 32k- w o rd 0e8000h - 0effffh 35 32k- w o rd 0e0000h - 0e7fffh 34 32k- w o rd 0d8000h - 0dffffh 33 32k- w o rd 0d0000h - 0d7fffh 32 32k- w o rd 0c8000h - 0cffffh 31 32k- w o rd 0c0000h - 0c7fffh 30 32k- w o rd 0b8000h - 0bffffh 29 32k- w o rd 0b0000h - 0b7fffh 28 32k- w o rd 0a8000h - 0affffh 27 32k- w o rd 0a0000h - 0a7fffh 26 32k- w o rd 098000h - 09ffffh 25 32k- w o rd 090000h - 097fffh 24 32k- w o rd 088000h - 08ffffh 23 32k- w o rd 080000h - 087fffh 22 32k- w o rd 078000h - 07ffffh 21 32k- w o rd 070000h - 077fffh 20 32k- w o rd 068000h - 06ffffh 19 32k- w o rd 060000h - 067fffh 18 32k- w o rd 058000h - 05ffffh 17 32k- w o rd 050000h - 057fffh 16 32k- w o rd 048000h - 04ffffh 15 32k- w o rd 040000h - 047fffh 14 32k- w o rd 038000h - 03ffffh 13 32k- w o rd 030000h - 037fffh 12 32k- w o rd 028000h - 02ffffh 11 32k- w o rd 020000h - 027fffh 10 32k- w o rd 018000h - 01ffffh 9 32k- w o rd 010000h - 017fffh 8 32k- w o rd 008000h - 00ffffh 7 4k- w o rd 007000h - 007fffh 6 4k- w o rd 006000h - 006fffh 5 4k- w o rd 005000h - 005fffh 4 4k- w o rd 004000h - 004fffh 3 4k- w o rd 003000h - 003fffh 2 4k- w o rd 002000h - 002fffh 1 4k- w o rd 001000h - 001fffh plane0 (parameter plane) 0 4k- w o rd 000000h - 000fffh figure 2.2 bottom parameter memory map - 7 - revi si on a3
W28F641B/t table 3. identifier codes and otp address for read operation c o d e a ddress [a 15 a0 ] da ta [dq15 dq0] notes manufacture code manufacture code 0000h 00b0h 1 t op parameter 00b0h 1, 2 device code bottom parameter 0001h 00b1h 1, 2 block is unlocked dq0 = 0 3 block is locked dq0 = 1 3 block is not locked-dow n dq1 = 0 3 block lock configuration code block is locked-dow n block address +2 dq1 = 1 3 device configuration code partition configuration regi ster 0 0 0 6 h p c r c 1 , 4 ot p lock 0080h ot p-lk 1, 5 ot p ot p 0 0 8 1 - 0 0 8 8 h ot p 1 , 6 notes: 1. the address a21 a16 are show n in below table for reading the manuf acturer code, device code, device configuration code and otp data. 2. bottom parameter device has its parameter blocks in the plane0 (the low e st address). top parameter device has its parameter blocks in the plane3 (the highest address). 3. block address = the beginning location of a block address w i thin the partition to w h ich the read identifier codes/otp command (90h) has been w r itten. dq15 dq2 are reserved for future implementation. 4. pcrc = partition configuration register code. 5. otp-lk = otp block lock configuration. 6. otp = otp block data. table 4. identifier codes and otp address fo r read operation on partition configuration (1) pa rtition configura tion register (2) p c r . 1 0 p c r . 9 p c r . 8 a ddress (64m-bit dev i ce) [a 21 a 16] 0 0 0 0 0 h 0 0 1 00h or 10h 0 1 0 00h or 20h 1 0 0 00h or 30h 0 1 1 00h or 10h or 20h 1 1 0 00h or 20h or 30h 1 0 1 00h or 10h or 30h 1 1 1 00h or 10h or 20h or 30h notes: 1. the address to read the identifier codes or otp data is dependent on the partition w h ich is selected w hen w r iting the read identifier codes/otp command (90h). 2. refer to table 12 for the par tition configuration register. - 8 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 - 9 - revi si on a3 customer programmable area lock bit (dq1) reserved for future implementation ( dq15-dq2 ) factory programmed area [a21-a0] 000088h 000085h 000084h 000081h 000080h customer programmable area f a ctory programmed area lock bit (dq0) figure 3. otp block address map for otp pr ogram (the area outside 80h~88h cannot be used.) table 5. bus operations (1, 2) m o d e n o t e #reset # c e # o e # w e a d d r e s s v pp dq0 15 read array 6 v ih v il v il v ih x x do ut output disable v ih v il v ih v ih x x h i g h z standby v ih v ih x x x x h i g h z r e s e t 3 v il x x x x x h i g h z read identifier codes/ot p 6 v ih v il v il v ih see t able 3, 4 x see t able 3, 4 read query 6,7 v ih v il v il v ih see appendix x see appendix w r ite 4,5,6 v ih v il v ih v il x x di n notes: 1. refer to dc characteristics. when v pp d v pplk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. #reset at v ss r 0.2v ensures the low e st pow er consumption. 4. command w r ites involving block erase, (page buffer) program or otp program are reliably executed w hen v pp = v pph1/2 and v dd = 2.7v to 3.6v. command w r ites involving full chip erase are reliably executed w hen v pp = v pph1 and v dd = 2.7v to 3.6v. 5. refer to table 6 for valid din during a w r ite operation. 6. never hold #oe low and #we low at the same timing. 7. refer to appendix for more information about query code.
W28F641B/t table 6. command definitions (11) first bus cycle second bus cycle comma nd bus cycles req?d. note oper (1) a ddr (2) d a t a o p e r (1) a ddr (2) d a t a (3) read array 1 w r ite pa f f h read identifier codes/ot p t 2 4 w r ite pa 90h read ia or oa id or od read query t 2 4 w r i t e p a 9 8 h r e a d q a q d read status register 2 w r ite pa 70h read pa srd clear status register 1 w r ite pa 50h block erase 2 5 w r ite ba 20h w r ite ba d0h f u ll chip erase 2 5, 9 w r ite x 30h w r ite x d0h p r o g r a m 2 5 , 6 w r i t e w a 40h or 10h write w a w d page buffer program t 4 5, 7 w r ite w a e8h w r ite w a n-1 block erase and (page buffer) program suspend 1 8 , 9 w r i t e p a b 0 h block erase and (page buffer) program resume 1 8 , 9 w r i t e p a d 0 h set block lock bit 2 w r ite ba 60h w r ite ba 01h clear block lock bit 2 10 w r ite ba 60h w r ite ba d0h set block lock-dow n bit 2 w r ite ba 60h w r ite ba 2f h ot p program 2 9 w r ite oa c0h w r ite oa od set partition configuration register 2 w r i t e pcrc 6 0 h w r i t e p c r c 0 4 h notes: 1. bus operations are defined in table 5. 2. all address w h ich is w r itten at the firs t bus cy cle should be the same as the addre ss w h ich is w r itten at the second bus cy c le. x = any valid address w i thin the device. pa = address w i thin the selected partition. ia = identifier codes address (see table 3 and table 4). qa = query codes address. refer to appendix for details. ba = address w i thin the block being erased, set/c leared block lock bit or set block lock-dow n bit. wa = address of memory location for the program command or the first address for the page buffer program command. oa = address of otp block to be read or programmed (see figure 3). pcrc = partition configuration regi ster code presented on the address a0 a15. 3. id = data read from identifier codes. (see table 3 and table 4). qd = data read from query database. refer to appendix for details. srd = data read from status register. see table 10 and t able 11 for a description of the status register bits. wd = data to be programmed at location wa. data is latched on the rising edge of #we or #ce (w hichever goes high first) during command w r ite cy cles. od = data w i thin otp block. data is latched on the rising edge of #we or #ce (w hichever goes high first) during command w r ite cy cles. n-1 = n is the number of the w o rds to be loaded into a page buffer. 4. follow i ng the read identifier codes/otp command, read oper ations access manufacturer code, device code, block lock configuration code, partition c onfiguration register code and the data w i thin otp block (see table 3 and table 4). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program cannot be executed w hen the selected block is locked. unlocked block can be erased or programmed w hen #reset is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. - 10 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 7. follow i ng the third bus cy cle, inputs the program sequential address and w r ite data of "n" times. finally , input the any val id address w i thin the target block to be programmed and the confirm command (d0h). refer to appendix for details. 8. if the program operation in one partition is suspended and the erase operation in other parti tion is also suspended, the suspended program operation should be re sumed first, and then the suspended eras e operation should be resumed next. 9. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted w h ile the block erase operation is being suspended. 10. follow i ng the clear block lock bit command, block w h ich is not locked-dow n is unlocked w hen #wp is v il . when #wp is v ih , lock-dow n bit is disabled and the selected block is unlocked regardless of lock-dow n configuration. 11. commands other than those show n above are reserved by winbond for future device impl ementations and should not be used. table 7. functions of block lock (5) and block lock-dow n current sta t e s t a t e # w p dq1 (1) dq0 (1) state name era se/progra m a llowed (2) [ 0 0 0 ] 0 0 0 u n l o c k e d y e s [001] ( 3 ) 0 0 1 l o c k e d n o [ 0 1 1 ] 0 1 1 l o c k e d - d o w n n o [ 1 0 0 ] 1 0 0 u n l o c k e d y e s [101] ( 3 ) 1 0 1 l o c k e d n o [110] ( 4 ) 1 1 0 lock-down d i s a b l e y e s [ 1 1 1 ] 1 1 1 lock-down d i s a b l e n o notes: 1. dq0 = 1: a block is locked; dq0 = 0: a block is unlocked. dq1 = 1: a block is locked-dow n; dq 1 = 0: a block is not locked-dow n. 2. erase and program are general terms, respectively , to ex press: block erase, full chip erase and (page buffer) program operations. 3. at pow er-up or device reset, all blocks default to locked state and are not locked-dow n, that is, [001] (#wp = 0) or [101] ( #wp = 1), regardless of the states before pow er-off or reset operation. 4. when #wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock functi on, w h ich is different from those described above. table 8. block locking state transitions upon command write (4) current sta t e result a fter lock comma nd written (next sta t e) s t a t e # w p dq1 dq0 se t loc k (1) clear l o c k (1) se t loc k - dow n (1) [ 0 0 0 ] 0 0 0 [ 0 0 1 ] no c h a n g e [011] ( 2 ) [ 0 0 1 ] 0 0 1 no change ( 3 ) [ 0 0 0 ] [ 0 1 1 ] [011] 0 1 1 no change no change no change [ 1 0 0 ] 1 0 0 [ 1 0 1 ] no c h a n g e [111] ( 2 ) [ 1 0 1 ] 1 0 1 no c h a n g e [ 1 0 0 ] [ 1 1 1 ] [ 1 1 0 ] 1 1 0 [ 1 1 1 ] no c h a n g e [111] ( 2 ) [111] 1 1 1 no change [110] no change - 11 - revi si on a3
W28F641B/t notes: 1. "set lock" means set block lock bit command, "clear lock" means clear block lock bit command and "set lock-dow n" means set block lock-dow n bit command. 2. when the set block lock-dow n bit command is w r itten to t he unlocked block (dq0 = 0), the corresponding block is locked- dow n and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command w r itten. 4. in this state transitions table, assumes that #wp is not changed and fixed v il or v ih . table 9. block locking state transitions upon #wp transition (4) current sta t e result a fter # w p tra n sition (next sta t e) previous sta t e s t a t e # w p d q 1 d q 0 #w p = 0 o 1 ( 1 ) #w p = 1 o 0 ( 1 ) - [ 0 0 0 ] 0 0 0 [ 1 0 0 ] - - [ 0 0 1 ] 0 0 1 [ 1 0 1 ] - [110] ( 2 ) [ 1 1 0 ] - other than [110] (2) [ 0 1 1 ] 0 1 1 [ 1 1 1 ] - - [ 1 0 0 ] 1 0 0 - [ 0 0 0 ] - [ 1 0 1 ] 1 0 1 - [ 0 0 1 ] - [ 1 1 0 ] 1 1 0 - [011] ( 3 ) - [ 1 1 1 ] 1 1 1 - [ 0 1 1 ] notes: 1. "#wp = 0 1" means that #wp is driven to v ih and "#wp = 1 0" means that #wp is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when #wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock confi guration commands are not w r itten in previous, current and next stat e. - 12 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 table 10. status register definition r r r r r r r r 1 5 1 4 1 3 1 2 1 1 1 0 9 8 w s m s b e s s b e f c e s p b p o p s v p p s p b p s s d p s r 7 6 5 4 3 2 1 0 sr.15 sr.8 = reserved fo r future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = blo c k erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = blo c k erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (pag e buffer) pro g r am and o t p pro g r am status (pbpo ps) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = (pag e buffer) pro g r am suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device pro t ect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved fo r future enhancements (r) no tes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition w hen the device is set to 2, 3 or 4 partitions configuration. if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-dow n bit, set partition configuration register attempt, an improper command sequence w a s entered. sr.3 does not provide a c ontinuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback w hen v pp z v pph 1 , v pph 2 or v pplk . sr.1 does not provide a conti nuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the sy stem, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after w r iting the read identifier codes/otp command indicates block lock bit status. sr.15 sr.8 and sr.0 are reserved for future use and should be masked out w hen polling the status register. check sr.7 to determine block er ase, full chip erase, (page buffer) program or otp program completion. sr.6 sr.1 ar e invalid w h ile sr.7 = "0". - 13 - revi si on a3
W28F641B/t table 11. extended status register definition r r r r r r r r 1 5 1 4 1 3 1 2 1 1 1 0 9 8 s m s r r r r r r r 7 6 5 4 3 2 1 0 xs r. 15 8 = reserved for fut ure enhancement s (r) x s r.7 = st at e machine st at us (sms) 1 = page buffer program available 0 = page buffer program not available x s r.6-0 = reserved for fut ure enhancement s (r) no tes: after issue a page buffer program command (e8h), xsr.7 = "1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15 8 and xsr.6 0 are reserved for future use and should be masked out w hen polling the ex tended status register. - 14 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 table 12. partition configur ation register definition r r r r r p c 2 p c 1 p c 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 pcr.15 11 = reserved for fut ure enhancement s (r) pcr.10 8 = part i t ion configurat ion (pc2-0) 000 = no partitioning. dual w o rk is not allow ed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0 1 and plane2 3 are merged into one partition respectively . 100 = plane 0 2 are merged into one partition. (default in a top parameter device) 011 = plane 2 3 are merged into one partition. t here are three partiti ons in this configuration. dual w o rk operation is available betw een any tw o partitions. 110 = plane 0 1 are merged into one partition. t here are three partiti ons in this configuration. dual w o rk operation is available betw een any tw o partitions. 101 = plane 1 2 are merged into one partition. t here are three partiti ons in this configuration. dual w o rk operation is available betw een any tw o partitions. 111 = there are four partitions in this configuration. each plane corresponds to eac h partition respectively . dual w o rk operation is available betw een any tw o partitions. pcr.7 0 = reserved fo r future enhancements (r) no tes: after pow er-up or device reset, pcr10 8 (pc2 0 ) i s s e t to "001" in a bottom parameter device and "100" in a top parameter device. see figure 4 for the detail on partition configuration. pcr.15 11 and pcr.7 0 are reserved for future use and should be masked out w hen checking the partition configuration register. pc2 pc1 pc0 pa rtitioning for dua l work pc2 pc1 p c0 pa rtitioning for dua l work pa r t it ion 0 p a r t it ion 2 pa r t it ion 1 pa r t it ion 0 0 0 0 0 1 1 pa r t it ion 1 pa r t it ion 0 pa r t it ion 2 pa r t it ion 1 pa r t it ion 0 0 0 1 1 1 0 pa r t it ion 1 p a r t it ion 0 pa r t it ion 2 pa r t it ion 1 pa r t it ion 0 0 1 0 1 0 1 pa r t it ion 1 p a r t it ion 0 pa rtition3 p a r tition2 pa rtition1 p a r tition0 1 0 0 1 1 1 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 plane3 plane2 plane1 plane0 figure 4. partition configuration - 15 - revi si on a3
W28F641B/t 4. electrical characteristics absolute maximum ratings* operating t e mperature during read, erase and program ..................................................................................... -40 q c to +85 q c (1) storage t e mperature during under bias .............................. ............................................................................... ... -40 q c to +85 q c during non bi as .............................. ................................................................................. . .. -65 q c to +125 q c voltage on any pin (except v dd and v pp ) ......... ........................................................................................ .. -0.5v to v dd +0.5v (2) v dd and v ddq supply volt age......................... ................................................................. ....... -0.2 v to +3.9v (2) v pp supply voltage ..................... ................................................................................ .... -0.2v to + 12.6v (2,3,4) output short circu it curr ent............. .............................................................................. ........ ...........100 ma (5) *w arning: stressing the device beyond t he "absolute m a xim u m ratings" m a y c ause perm anent dam age. these are stress ratings only. operation beyond the "operating c onditions" is not recom m ended and extended exposure beyond the "o perating conditions" m a y affect device reliability. notes: 1. operating temperature is for extended temper ature product defined by this specification. 2. all specified voltages are w i th respect to v ss . minimum dc voltage is -0.5v on input/output pins and -0.2v on v dd and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20 ns. ma ximum dc voltage on input/output pins is v dd +0.5v, w h ich, during transitions, may overshoot to v dd +2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +13.0v for periods <20 ns. 4. v pp erase/program voltage is normally 2.7v to 3.6v. apply i ng 11.7v to 12.3v to v pp during erase/program can be done for a max i mum of 1,000 cy cles on the main blocks and 1,000 cy cles on the parameter blocks. v pp may be connected to 11.7v to 12.3v for a total of 80 hours maximum. 5. output shorted for no more than one second. no more than one output shorted at a time. operating conditions pa ra m e t e r s y m . m i n . t y p . ma x . u n i t n o t e operating t e mperatur e t a - 4 0 + 2 5 + 8 5 q c v dd supply voltage v dd 2 . 7 3 . 0 3 . 6 v 1 i/o supply voltage v ddq 2 . 7 3 . 0 3 . 6 v 1 v pp voltage w hen used as a logic control v pph1 1 . 6 5 3 . 0 3 . 6 v 1 v pp supply voltage v pph2 1 1 . 7 1 2 1 2 . 3 v 1 , 2 main block erase cy cling: v pp = v pph1 1 0 0 , 0 0 0 cy c l e s parameter block erase cy cling: v pp = v pph1 1 0 0 , 0 0 0 cy c l e s main block erase cy cling: v pp = v pph2 , 80 hrs. 1 , 0 0 0 cy c l e s parameter block erase cy cling: v pp = v pph2 , 80 hrs. 1 , 0 0 0 cy c l e s max i mum v pp hours at v pph2 8 0 h o u r s notes: 1. see dc characteristics tables for voltage range-specific specification. 2. apply i ng v pp = 11.7v to 12.3v during a erase or program can be done for a maximum of 1,000 cy cles on the main blocks and 1,000 cy cles on the parameter blocks. a permanent connection to v pp = 11.7v to 12.3v is not allow ed and can cause damage to the device. - 16 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 capacitance (1) t a = +25 q c, f = 1 mhz pa ra m e t e r s y m . t y p . ma x . u n i t c o n d i t i o n input capacitance c in 6 8 pf v in = 0.0v output capacitance c out 1 0 1 2 pf v out = 0.0v note: sampled, not 100% tested. ac input/output test conditions vddq 0.0 input vddq/2 output test points vddq/2 ac test inputs are driven at v ddq (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v ddq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are w hen v dd = v dd (mi n ). figure 5. transient input/output reference waveform for v dd = 2.7v to 3.6v vddq(min)/2 includes jig capacitance 1n914 device under test out =3.3k ohm r l c l c l figure 6. transient equiva lent testing load circuit table 13. configuration capacitance loading value test configuration c l (pf) v dd = 2.7v to 3.6v 50 - 17 - revi si on a3
W28F641B/t dc characteristics v dd = 2.7v to 3.6v pa ra m e t e r s y m . t est c o n d i t i o n s m i n . t y p . ma x . unit input load current (note 1) i li - 1 . 0 + 1 . 0 p a output leakage current (note1) i lo v dd = v dd max ., v ddq = v ddq max ., v in /v out = v ddq or v ss - 1 . 0 + 1 . 0 p a v dd standby current (note 1) i ccs v dd = v dd max . #ce = #reset = v ddq r 0.2v, #w p = v ddq or v ss 4 2 0 p a v dd automatic pow e r saving current (note 1, 4) i cca s v dd = v dd max . #ce = v ss r 0.2v, #w p = v ddq or v ss 4 2 0 p a v dd reset pow e r-dow n current (note 1) i ccd #reset = v ss r 0.2v 4 2 0 p a average v dd read current normal mode (note1, 7) 1 5 2 5 m a average v dd read current page mode (note1, 7) 8 w o rd read i ccr v dd = v dd max ., #ce = v il , #oe = v ih , f = 5 mhz 5 1 0 m a v pp = v pph 1 2 0 6 0 m a v dd (page buffer) program current (note 1, 5, 7) i ccw v pp = v pph 2 1 0 2 0 m a v pp = v pph 1 1 0 3 0 m a v dd block erase, f u ll chip erase current (note 1, 5, 7) i cce v pp = v pph 2 1 0 3 0 m a v dd (page buffer) program or block erase suspend current (note 1, 2, 7) i ccw s i cce s #ce = v ih 1 0 2 0 0 p a v pp standby or read current (note 1, 6, 7) i pps i ppr v pp d v dd 2 5 p a v pp = v pph 1 2 5 p a v pp (page buffer) program current (note 1, 5, 6, 7) i ppw v pp = v pph 2 1 0 3 0 m a v pp = v pph 1 2 5 p a v pp block erase, f u ll chip erase current (note 1, 5, 6, 7) i ppe v pp = v pph 2 5 1 5 m a v pp = v pph 1 2 5 p a v pp (page buffer) program suspend current (note 1, 6, 7) i ppw s v pp = v pph 2 1 0 2 0 0 p a v pp = v pph 1 2 5 p a v pp block erase suspend current (note 1, 6, 7) i ppes v pp = v pph 2 1 0 2 0 0 p a - 18 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 dc characteristics, continued v dd = 2.7v 3.6v pa ra m e t e r s y m . test conditions min. ty p. max. unit input low voltage (note 5) v il - 0 . 4 0 . 4 v input high voltage (note 5) v ih 2 . 4 v ddq +0 .4 v output low voltage (note 5) v ol v dd = v dd min., v ddq = v ddq min., i ol = 100 p a 0 . 2 v output high voltage (note 5) v oh v dd = v dd min., v ddq = v ddq min., i oh = -100 p a v ddq -0.2 v v pp lockout during normal operations (note 3, 5, 6) v pplk 0 . 4 v v pp during block erase, f u ll chip erase, (page buffer) program or ot p program operations (note 6) v pph 1 1 . 6 5 3 . 0 3 . 6 v v pp during block erase, (page buffer) program or ot p program operations (note 6) v pph 2 1 1 . 7 1 2 1 2 . 3 v v dd lockout voltage v lko 1 . 5 v notes: 1. all currents are in rms unless otherw i se noted. ty pical values are the reference values at v dd = 3.0v and t a = +25 q c unless v dd is specified. 2. i ccw s and i cce s are specified w i th the device de-selected. if read or (page buffer) program is executed w h ile in block erase suspend mode, the device's current draw is the sum of i cce s and i ccr or i ccw . if read is executed w h ile in (page buffer) program suspend mode, the device?s current draw is the sum of i ccw s and i ccr . 3. block erases, full chip erase, (page buffe r) program and otp program are inhibited w hen v pp d v pplk , and not guaranteed in the range betw een v pplk (max.) and v pph1 (min.), betw een v pph1 (max.) and v pph2 (min.) and above v pph2 (max.). 4. the automatic pow e r savings (aps) feature automatically plac es the device in pow er save mode after read cy cle completion. standard address access timings (t avqv ) provide new data w hen address are changed. 5. sampled, not 100% tested. 6. v pp is not used for pow er supply pin. with v pp d v pplk , block erase, full chip erase, (page buffer) program and otp program cannot be executed and should not be attempted. apply i ng 12v 0.3v to v v pp provides fast erasing or fast programming mode. in this mode, v pp is pow er supply pin and supplies the memory cell current for block erasing and (page bu ffer) programming. use similar pow er supply trace w i dths and lay out considerations given to the v dd pow er bus. apply i ng 12v 0.3v to v pp during erase/program can only be done for a maximum of 1,000 cy cles on each block. v pp may be connected to 12v 0.3v for a total of 80 hours maximum. 7. the operating current in dual w o rk is the sum of t he operating current (read, erase, program) in each plane. - 19 - revi si on a3
W28F641B/t ac characteristics - read-only operations(1) v dd = 2.7v to 3.6v, t a = -40 q c to +85 q c pa ra m e t e r s y m . m i n . ma x . u n i t read cy cle t i me t avav 8 0 n s address to output delay t avqv 8 0 n s #ce to output delay (note 3) t elqv 8 0 n s page address access t i me t apa 3 5 n s #oe to output delay (note 3) t glqv 2 0 n s #reset high to output delay t ph qv 1 5 0 n s #ce or #oe to output in high z , w h ichever occurs f i rst (note 2) t eh qz, t ghqz, 2 0 n s #ce to output in low z (note 2) t elqx 0 n s #oe to output in low z (note 2) t glqx 0 n s output hold from first occurring address, #ce or #oe change (note 2) t oh 0 n s address setup to #ce, #oe, going low for reading status register (note 4,6) t avel, t avgl 1 0 n s address hold from #ce, #oe, going low for reading status register (note 5,6) t elax , t glax 3 0 n s #ce, #oe pulse w i dth high for readi ng status register (note 6) t eh el, t ghgl 3 0 n s notes: 1. see ac input/output reference waveform for timi ng measurements and maximum allow able input slew rate. 2. sampled, not 100% tested. 3. #oe may be delay ed up to t elqv to t glqv after the falling edge of #ce w i thout impact to t elqv . 4. address setup time (t avel to t avgl ) is defined from the falling edge of #ce or #o e (w hichever goes low last). 5. address hold time (t elax to t glax ) is defined from the falling edge of #ce or #o e (w hichever goes low last). 6. specifications t avel , t avgl , t elax , t glax , and t eh el, , t ghgl for read operations apply to only status register read operations. - 20 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 v ih v il a21-0(a) #oe(g) #we(w) #ce(e) v ih v il vaild address v ih v il v ih v il v ih v il dq15-0 (d/q) v oh v ol #reset(p) high z t glqv t elqx t glqx t oh valid output t avav t elax t phqv t ghqz t ehqz t avqv t ehel t avel t glax t avgl t ghgl t elqv figure 7. ac waveform for single asy n chronous read operations from status register, identifier codes, otp block or query code - 21 - revi si on a3
W28F641B/t v ih v il #oe(g) #we(w) #ce(e) v ih v il v ih v il v ih v il dq15-0 (d/q) v oh v ol #reset(p) high z t glqv t elqx t glqx t oh t avqv t elqv t phqv a2-0(a) v ih v il valid address t ghqz t ehqz a21-3(a) v ih v il valid address valid address valid address valid address valid address valid address valid address valid address t apa figure 8. ac waveform for asy n chronous page mode read o p erations from main blocks or parameter blocks - 22 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 ac characteristics - write operations (1, 2) v dd = 2.7v to 3.6v, t a = -40 q c to +85 q c pa ra m e t e r s y m b o l m i n . ma x . u n i t write cy cle t i me t avav 8 0 n s #reset high recovery to #we(#ce) going low (note 3) t ph w l (t ph el ) 1 5 0 n s #ce(#w e) setup to #w e(#ce) going low t elw l (t wl e l ) 0 n s #w e(#ce) pulse w i dth (note 4) t wl wh (t eleh ) 5 0 n s data setup to #w e(#ce) going high (note 8) t dv w h (t d veh ) 4 0 n s address setup to #w e(#ce) going high (note 8) t avw h (t aveh ) 5 0 n s #ce(#w e) hold from #w e(#ce) high t wh e h (t eh w h ) 0 n s data hold from #w e(#ce) high t w hdx (t e hdx ) 0 n s address hold from #w e(#ce) high t wh a x (t eh ax ) 0 n s #w e(#ce) pulse w i dth high (note 5) t wh wl (t eh el ) 3 0 n s #w p high setup to #w e(#ce) going high (note 3) t sh w h (t sh eh ) 0 n s v pp setup to #w e(#ce) going high (note 3) t vvw h (t vveh ) 2 0 0 n s w r ite recovery before read t wh g l (t eh gl ) 3 0 n s #w p high hold from valid srd (note 3,6) t qvsl 0 n s v pp hold from valid srd (note 3,6) t qvvl 0 n s #w e(#ce) high to sr.7 going "0" (note 3,7) t w hr0 (t e hr0 ) t avqv + 5 0 n s notes: 1. the timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and ot p program operations are the same as during read-only operatio ns. refer to ac characteristics for read-only operations. 2. a w r ite operation can be initiated and terminated w i th either #ce or #we. 3. sampled, not 100% tested. 4. write pulse w i dth (t wp ) is defined from the falling edge of #ce or #we (w hich ever goes low last) to the rising edge of #ce or #we (w hichever goes hi gh first). hence, t wp = t wl wh = t eleh = t wl e h = t elw h . 5. write pulse w i dth high (t wp h ) is defined fr om the r i sing edge of #ce or #we ( w hichever goes high fir s t) to the falling edge of #ce or #we (w hichever goes low last). hence, t wp h = t wh wl = t eh el = t wh e l = t eh w l . 6. v pp should be held at v pp = v pph 1/2 until determination of block erase, (p age buffer) program or otp program success (sr.1/3/4/5 = 0) and held at v pp = v pph 1 until determination of full chip erase success (sr.1/3/5 = 0). 7. t w hr0 (t e hr0 ) after the read query or read identifier codes/otp command = t avqv +100 ns. 8. refer to table 6 for valid address and data for block erase, full chip erase, (page buffer) program, otp program or lock bit configuration. - 23 - revi si on a3
W28F641B/t a21-0(a) v ih v il t avav #we(w) v ih v il dq15-0(d/q) v ih d in valid srd v il ("0") #wp(s) ih il v v sr.7(r) ("1") #reset(p) ih il v v pph1,2 v pplk v il v (v) v pp note 1 note 2 note 3 note 4 note 5 #ce(e) v ih v il #oe(g) v ih v il note 5,6 d in note 5,6 vvwh t vveh (t ) qvvl t shwh t sheh (t ) qvsl t whr0 t ehr0 (t ) (t ) whqv1,2,3 t ehqv1,2,3 (t ) dvwh t dveh (t ) whdx t ehdx (t ) wlwh t eleh (t ) phwl t phel (t ) whwl t ehel (t ) elwl t wlel (t ) wheh t ehwh (t ) whgl t ehgl (t ) whax t ehax (t ) avwh t aveh valid address valid address valid address figure 9. ac waveform for write operations notes: 1. v dd pow er-up and standby . 2. write each first cy cle command. 3. write each second cy cle command or valid address and data. 4. automated erase or program delay . 5. read status register data. 6. for read operation, #oe and #ce must be driven active, and #we de-asserted. - 24 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 reset operations ih il v v #reset(p) high z plrh t (c)#reset rising timing 2vph t v dd ih il v v #reset(p) plph t (a)reset during read array mode dq15-0(d/q) oh ol v v phqv t valid output ih il v v #reset(p) plph t abort complete sr.7="1" phqv t (b)reset during erase or program mode dq15-0(d/q) oh ol v v high z valid output dq15-0(d/q) oh ol v v high z valid output phqv t v dd (min) vss vhqv t figure 10. ac waveform for reset operation reset ac specifications v dd = 2.7v to 3.6v, t a = -40 q c to +85 q c pa ra m e t e r s y m . m i n . ma x . u n i t #reset low to reset during read (#reset should be low during pow er-up.) (note 1, 2, 3) t plph 1 0 0 n s #reset low to reset during erase or program (note 1, 3, 4) t plrh 2 2 p s v dd 2.7v to #reset high (note 1, 3, 5) t 2vph 1 0 0 n s v dd 2.7v to output delay (note 3) t vhqv 1 m s - 25 - revi si on a3
W28F641B/t notes: 1. a reset time, t ph qv , is required from the later of sr.7 going "1" or #reset going high until outputs are valid. refer to ac characteristics - read-only operations for t ph qv . 2. t plph is <100 ns the device may still reset but this is not guaranteed. 3. sampled, not 100% tested. 4. if #reset asserted w h ile a block erase, full chip erase, ( page buffer) program or o t p program operation is not executing, the reset w ill complete w i thin 100 ns. 5. when the device pow er-up, holding #reset low minimum 100ns is required after v dd has been in predefined range and also has been in stable there. block erase, full chip erase, (page buffer) program and otp program performance (3) v dd = 2.7v to 3.6v, t a = -40 q c to +85 q c v pp = v pph1 (in system) v pp = v pph2 (in ma nufa c turing) pa ra m e t e r s y m . pa ge buffer comma nd is used or not used min. typ. (1 ) ma x. (2 ) m i n . t y p . (1 ) ma x. (2 ) unit not used 0.05 0.3 0.04 0.12 s 4k-word parameter block program t i me (note 2) t wp b u s e d 0 . 0 3 0 . 1 2 0 . 0 2 0 . 0 6 s not used 0.38 2.4 0.31 1.0 s 32k-w ord main block program t i me (note 2) t wm b u s e d 0 . 2 4 1 . 0 0 . 1 7 0 . 5 s not used 11 200 9 185 p s w o rd program t i me (note 2) t wh q v 1 / t ehqv1 u s e d 7 1 0 0 5 9 0 p s ot p program t i me (note 2) t wh o v 1 / t ehov1 not used 36 400 27 185 p s 4k-word parameter block erase t i me (note 2) t wh q v 2 / t ehqv2 - 0 . 3 4 0 . 2 4 s 32k-w ord main block erase t i me (note 2) t wh q v 3 / t ehqv3 - 0 . 6 5 0 . 5 5 s f u ll chip erase t i me (note 2) 80 700 s (page buffer) program suspend latency t i me to read (note 4) t w hrh1/ t ehrh1 - 5 1 0 5 1 0 p s block erase suspend latency t i me to read (note 4) t w hrh2/ t ehrh2 - 5 2 0 5 2 0 p s latency t i me from block erase resume command to block erase suspend command (note 5) t eres - 5 0 0 5 0 0 p s notes: 1. ty pical values measured at v dd = 3.0v, v pp = 3.0v or 12v, and t a = +25 q c. assumes corresponding lock bits are not set. subject to change based on dev ice characterization. 2. excludes external sy stem-level overhead. 3. sampled, but not 100% tested. - 26 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 4. a latency time is required from w r iting suspend command (#we or #ce going high) until sr.7 going "1". 5. if the interval time from a block erase resume comm and to a subsequent block erase suspend command is shorter than t er es and its sequence is repeated, the block erase operation may not be finished. 5. additional information recommended operating conditions at device pow e r-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. v ih v il dd v ih v il v ih v il #oe valid address v dd v vss (min) t vr t 2vph t phqv #reset (p) *1 vpp (v) vss v pph1/2 a ddress v ih v il (a) t t r or f t t r or f t avqv #ce (e) t r t f t elqv t glqv #we (w) v ih v il (g) t f t r #wp (s) v ih v il data (d/q) v oh v ol valid output high z *1 to prevent the unw anted w r ites, sy stem desi gners should consider the design, w h ich applies v pp to 0v during read operations and v pph 1/2 during w r ite or erase operations. figure a-1. ac timing at device pow e r-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specificatio ns? described in specifications for the supply voltage range, the operating temperature and the ac spec ifications not show n in the next page. - 27 - revi si on a3
W28F641B/t rise and fall time p a r a m e t e r s y m b o l m i n . m a x . u n i t v dd rise time (note 1) t vr 0 . 5 3 0 0 0 0 p s/ v input signal rise time (note1, 2) t r 1 p s/ v input signal fall time (note1, 2) t f 1 p s/ v notes: 1. sampled, not 100% tested. 2. this specification is appli ed for not only the device pow er-up but also the normal operations. glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). t he acceptable glitch noises are illustrated in figure a-2 (a). input singal v ih (min.) input singal v ih (min.) v il (max.) input singal v il (max.) input singal ( a ) acce p table glitch noises (b) not acceptable glitch noises figure a-2. waveform for glitch noises see the "dc characteristics" de scribed in specifications for v ih (min.) and v il (max.). - 28 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 6. ordering information pa rt no. a ccess time ( n s ) opera t ing tempera t ure ( q c) boot block pa cka ge w 28f 641bt 8 0 l 8 0 -40o c to 85 q c bottom boot 48-pin t s op w 28f 641bb80l 80 -40o c to 85o c bottom boot 48-ball t f bga w 28f 641t t 8 0 l 8 0 -40o c to 85 q c t op boot 48-pin t s op w 28f 641t b80l 80 -40o c to 85o c t op boot 48-ball t f bga notes: 1. winbond reserves the right to make changes to its products w i thout prior notice. 2. purchasers are responsible for performing appropriate qualit y assurance testing on products intended for use in applications w here personal injury might occur as a consequence of product failure. - 29 - revi si on a3
W28F641B/t 7. package dimensions 48-pin standard thin small outline package (measured in millimeters) 0.020 0.004 0.007 0.037 0.002 min. 0.60 y l l1 c 0.50 0.10 0.70 0.21 millimeter a a2 b a1 0.95 0.17 0.05 sym. min. 1.20 0.27 1.05 1.00 0.22 max. nom. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 nom. inch max. e h d 0 5 0 5 e d 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.020 0.50 t e 1 48 b e d y a1 a a2 l1 l c h d t 48-ball tfbga (8 mm x 11 mm) (measurements in millimeters) symbol a a1 d d2 e e2 y b e millimeter -- 1.05 min. nom. max. 0.20 0.25 0.30 5.25 basic 3.75 basic 0.10 basic 0.37 0.40 0.43 0.75 basic inch -- 0.042 min. nom. max. 0.008 0.010 0.012 7.80 8.00 8.20 0.312 0.320 0.328 0.210 0.150 basic 0.004 basic 0.015 0.016 0.017 0.030 basic control dimensions are in millimeters a b c d e f 1 2 3 4 5 6 d d2 e e2 e e seating plane a1 a b 10.80 11.00 11.20 0.400 0.440 0.480 g h - 30 -
W28F641B/t publ i c at i on rel e ase dat e : march 27, 2003 - 31 - revi si on a3 8. version history v e r s i o n d a t e p a g e d e s c r i p t i o n a1 jan. 7, 2003 - initial issued a2 feb. 17, 2003 29 modify tfbga package dimension drawing a3 march 27, 2003 all typo correction headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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